The present invention relates to a gate driver having level shift circuit for driving the gate of a power semiconductor device.
Many low voltage electronic circuits, e.g., MOSFET devices, are used to drive high voltage switching transistors, e.g., power MOSFETs, insulated gate bipolar transistor devices (IGBTs), gate controlled thyristors, and the like. A power semiconductor switch or device is switched from a nonconducting state to a conducting state by raising the gate-source voltage from below to above a threshold voltage. As used herein, the term xe2x80x9cpower devicexe2x80x9d or xe2x80x9cpower semiconductor devicexe2x80x9d refers to any power MOSFET, IGBT, thyristor, or the like.
One or more low voltage transistors, coupled to an output node of the gate driver, apply appropriate voltages to the gate or control terminal of the power device to turn on or turn off the power device. When the power device is an N-channel metal oxide semiconductor field effect transistor (NMOSFET), the device is turned on by applying a high voltage to the gate of the power switch and turned off by applying a low voltage to the gate. In contrast, if the power device is a P-channel metal oxide semiconductor field effect transistor (PMOSFET), the device is turned on by applying a low voltage to the gate of the power switch and turned off by applying a high voltage to the gate. Unless otherwise explained, power devices, as used herein, refer to in N type devices for ease of illustration.
Generally, a gate driver includes a level shifting circuit for shifting the potential of a small control signal to a higher voltage level that is more suitable for turning on the power device. The gate driver may be packaged as a single device having a high side portion and a low side portion, where the high side is used to turn on or off a high side switch or transistor of the power device and the low side is used to turn on or off a low side switch or transistor of the power device. The high side switch has a drain coupled to a high voltage source, e.g., 1000 volts, while the low side switch has a drain coupled to a lower voltage source, e.g., a source of the high side switch.
In one embodiment, a power module includes a power semiconductor device having a first terminal, a second terminal, and a third terminal. The second terminal is a control terminal to regulate flow of electricity between the first and third terminals. A gate driver has an output node coupled to the second terminal of the power device to provide gate control signals to the power semiconductor device. The gate driver includes a gate control signal generator having a first input and a second input and a first sub-circuit having a first signal path and a second signal path that are suitable for transmitting signals. The first and second signal paths are coupled to the first input of the gate control signal generator. The second signal path is configured to provide a signal to the first input with a reduced signal delay. The gate driver further includes a second sub-circuit coupled to the second input of the gate control signal generator.
In one embodiment, a method for forming a gate driver configured to drive a power semiconductor device includes providing a substrate having an upper surface; forming a first conductive region on a portion of the upper surface of the substrate; forming a first dielectric layer overlying the first conductive region; forming a conductive layer provided over the first conductive region and at least a portion of the first dielectric layer, the conductive layer configured to be a resistor; forming a first conductive structure electrically coupled to the first conductive region and the conductive layer; and forming a second conductive structure electrically coupled to the conductive layer. The first conductive region, the conductive layer, and the at least portion of the first dielectric layer together form a first capacitor. The first conductive region, the second conductive structure, and a portion of the first dielectric layer form a second capacitor.
In another embodiment, a method for forming a gate driver configured to drive a power semiconductor device includes providing a substrate having an upper surface; forming a conductive region on a portion of the upper surface of the substrate; forming a dielectric layer overlying the conductive region; forming a first conductive layer provided over the conductive region and at least a portion of the dielectric layer; patterning the first conductive layer to provide the first conductive layer with a given resistance value; forming a second conductive layer over the dielectric layer and electrically coupled to the conductive region and first conductive layer; and patterning the second conductive layer to provide an input node that is coupled to a first portion of the resistor and an output node that is coupled to a second portion of the resistor. The input node is configured to receive a control signal from a control signal generator and the output node is configured to receive the control signal from the input node via the resistor. The conductive region, the first conductive layer, and the at least portion of the dielectric layer together form a first capacitor.